Stress incorporation in semiconductor devices

ABSTRACT

Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. Non-Provisional PatentApplication No. 17/000,546, filed Aug. 24, 2020, the content of which ishereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

The present technology relates to methods for semiconductor processing.More specifically, the present technology relates to methods forincorporating increased stress in doped regions of semiconductordevices.

BACKGROUND

Integrated circuits are made possible by processes which produceintricately patterned material layers on substrate surfaces. Producingpatterned material on a substrate requires controlled methods forforming and removing material. As device sizes continue to reduce, filmcharacteristics may lead to larger impacts on device performance.Materials used to form layers of materials may affect operationalcharacteristics of the devices produced. As material thicknessescontinue to reduce, as-deposited characteristics of the films may have agreater impact on device performance.

Thus, there is a need for improved methods that can be used to producehigh quality devices and structures. These and other needs are addressedby the present technology.

SUMMARY

Embodiments of the present technology include processing methods toincorporate additional stress in a semiconductor substrate using asacrificial stressed material. Exemplary locations for incorporating theadditional stress include regions of semiconductor material having anincorporated dopant, such as a source region, a drain region, and achannel region under a gate of a semiconductor transistor. In someembodiments, the methods may include depositing a stressed material onan adjacent layer that is between the stressed material and thesemiconductor material having an incorporated dopant. The adjacent layermay be characterized by increased stress after the deposition of thestressed material. The method may further include heating the stressedmaterial and the adjacent layer. In some embodiments, the heating may bedone with a rapid thermal process that raises the temperature of thematerial to several hundred degrees Celsius in less than or about onesecond. Embodiments of these rapid thermal processes include a spikeanneal that heats the stressed material and adjacent layer at a heatingrate greater than or about 200° C. The stressed material may be removedfrom the adjacent layer following the heating. As a result of theheating, the adjacent layer retains at least a portion of the increasedstress after the removal of the stressed material. In some embodiments,the adjacent layer retains greater than or about 0.1% of the increasedstress after the removal of the stressed material.

Embodiments of these methods include a stressed material made from adielectric material or an electrically-conductive material. Additionalembodiments include making a stressed, electrically-conductive materialfrom one or more of tungsten, cobalt, copper, and aluminum. Embodimentsfurther include the stressed material having a stress level greater thanor about 1 GPa. In some embodiments, the adjacent layer upon which thestressed material is deposited may be characterized by a nominalviscosity less than or about 1.5 × 10⁶ cP at 25° C. In furtherembodiments, at least a portion of the sacrificial stressed material maybe replaced by a second material with low stress that makes contact withthe adjacent layer. Embodiments include the second material being aconductive material such as a conductive metal. In some embodiments, thestressed material is a dielectric material that is replaced by a secondmaterial made of a conductive metal characterized by about neutralstress (e.g., stress of less than or about 0.1 MPa).

Embodiments of the present technology also include processing methodsthat deposit a stressed material on an adjacent layer, where theadjacent layer is characterized by a pre-deposition stress level beforethe stressed material is deposited on the adjacent layer. The methodsmay also include annealing the stressed material and the adjacent layerat a heating rate greater than or about 150° C./second. After theanneal, at least a portion of the stressed material may be replaced witha conductive material, and at least some of the conductive material maybe in contact with the adjacent layer. The conductive material may becharacterized by approximately neutral stress, and the adjacent layermay have a post-anneal stress that is greater than the pre-depositionstress as a result of the sacrificial stressed material imparting stressto the adjacent layer through the anneal. In some embodiments, theadjacent layer may have a post-anneal stress that is at least ten timesgreater than the stress of the conductive material.

Embodiments of these methods include a stressed material made from adielectric material or an electrically-conductive material. Embodimentsfurther include the stressed material having a stress level greater thanor about 1 GPa. Additional embodiments include making the conductivematerial from one or more of tungsten, cobalt, copper, and aluminum. Insome embodiments, the adjacent layer is formed between the stressedmaterial and the semiconductor material having an incorporated dopant.In embodiments, the semiconductor material having an incorporated dopantmay be a source region, a drain region, or a gate channel region of thesemiconductor transistor.

Embodiments of the present technology may further include asemiconductor structure. The structure may include a conductive layercharacterized by a first tensile stress. The structure may furtherinclude an intermediate (adjacent) layer in contact with the conductivelayer. The intermediate layer may be characterized by a second tensilestress at least ten times the first tensile stress. The structure maystill further include a semiconductor material having an incorporateddopant. The intermediate layer may be disposed between the conductivelayer and the semiconductor material having the incorporated dopant.

Embodiments of the structure include the conductive layer characterizedby a first tensile stress less than 0.1 MPa. Embodiments further includethe conductive layer being made from at least one of tungsten, cobalt,copper, and aluminum. Embodiments also include the intermediate layercharacterized by a second tensile stress of greater than or about 1 MPa.In some embodiments, the intermediate layer may be made from siliconoxide or silicon nitride. In further embodiments, the semiconductormaterial having an incorporated dopant may include a source region, adrain region, or a channel region of a semiconductor transistor.

Such technology may provide numerous benefits over conventionaltechniques. For example, embodiments of the present technology producedesired levels of stress in the channel region of a semiconductortransistor without changing the composition of the adjacent source anddrain regions. In addition, the present technology originates thechannel region stress from a removable stressed material which leavesbehind an imprint of the stress on adjacent layers that can transmit thestress to the channel region. Because the stressed material isremovable, it can be deposited with more defects that a permanentmaterial. It can also be selected for its ability to impart stresswithout concern for other characteristics such as conductivity orhermeticity, among other ancillary characteristics. These and otherembodiments, along with many of their advantages and features, aredescribed in more detail in conjunction with the below description andattached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the disclosedtechnology may be realized by reference to the remaining portions of thespecification and the drawings.

FIG. 1 shows operations in a semiconductor processing method accordingto some embodiments of the present technology.

FIGS. 2A-2C show cross-sectional views of exemplary semiconductorstructures according to some embodiments of the present technology.

Several of the figures are included as schematics. It is to beunderstood that the figures are for illustrative purposes, and are notto be considered of scale unless specifically stated to be of scale.Additionally, as schematics, the figures are provided to aidcomprehension and may not include all aspects or information compared torealistic representations, and may include exaggerated material forillustrative purposes.

In the appended figures, similar components and/or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a letter thatdistinguishes among the similar components. If only the first referencelabel is used in the specification, the description is applicable to anyone of the similar components having the same first reference labelirrespective of the letter.

DETAILED DESCRIPTION

The present technology includes process methods for forming stress in achannel region of a semiconductor transistor, such as n-channel andp-channel MOSFETs, FinFETs, gate-all-around FETs, and nanosheet FETs,among other types of transistors. In conventional process methods, thestress level in the transistor channel may be controlled by altering thecomposition of the semiconductor materials in the channel, as well asthe compositions of the materials in the adjacent source and drainregions. In many instances, the changes to the compositions of thesedoped regions of the transistor to give the channel region a desiredamount of stress can lead to less desirable transistor performance inother respects, such as a lower thermal budget, and an increasedresistance at the interface between the contact and the doped region,among other problems. Controlling channel region stress by altering thecomposition of the doped regions also limits the types of materials thatcan be used in the doped regions. For example, modern PMOS transistorsoften use a doped silicon-germanium (SiGe) semiconductor in the dopedregions of the transistor. When the Ge-to-Si ratio gets too high,lattice mismatches create faults in the material that can reduce thechannel region stress below an acceptable level.

Another conventional method for increasing the stress in a channelregion of a transistor is depositing a stressed conductive material inthe contact trench above the channel region. The stress from theconductive material is transmitted down to impart the required stress inthe doped material of the channel region. These conventional methodsalso require careful selection and deposition of the conductive materialin the contact trench to meet the stress requirements as well as theelectrical conductivity, chemical reactivity, hermeticity, thermalbudget, and other requirements for the material. In many instances,there must be a compromise in selecting a conductive material with lessthan ideal characteristics in some respects in order to satisfy thestress requirement. The changes in the deposition method or compositionof the stressed material to create additional stress can diminish theperformance of the material in other respects, such as electricalconductivity.

The present technology includes embodiments of methods to impart stressto a channel region of a transistor without having to alter thecompositions of the doped regions of the transistor or leave high-stressconductive materials in the contact trenches. In embodiments of thepresent technology, the stresses originate with the deposition of asacrificial stressed material on one or more layers of material that areadjacent to one or more doped region of the transistor. The stressedmaterial may initially impart stress to the one or more layers, which inturn may transmit a portion of the stress to the channel region of thetransistor. A heating operation may be performed so that at least aportion of the stress from the stressed material is retained by the oneor more layers adjacent to the doped regions after the stressed materialis removed. Embodiments of the heating operation include a rapid thermalanneal that heats the stressed material deposited on the one or morelayers at a rapid heating rate of, for example, greater than or about150° C./second.

The rapid heating leaves the materials in the one or more adjacentlayers in a disordered state at the atomic level, and traps at least aportion of the stress in these layers that was initially imparted bycontact with the stressed material. In one sense, the rapid heating stepmay be said to cause the one or more adjacent layers to “memorize” thestress from the stressed material. Following the heating operation, theone or more adjacent layers permanently retain at least a portion of thestress from the stressed material, and they can impart at least some ofthat memorized stress to the channel region of the transistor after thestressed material is removed. In contrast, a conventional thermal anneal(e.g., an anneal conducted at a heating rate of less than or about 10°C./second) is believed to give the material in the one or more adjacentlayers time to come to a more ordered state at the atomic level, whichcan reduce the retained stress in the layers. Conventional thermalanneals can also take longer than rapid thermal anneals, which increasethe process time and reduces production efficiencies. Additionally,conventional annealing that uniformly heats the entire substrate mayaffect thermal budget of incorporated materials. A more localized rapidthermal process such as laser spike annealing may afford the ability toanneal and temperatures well above a thermal budget, while limiting anyimpact on materials that may otherwise be compromised at thoseprocessing temperatures.

The present technology includes embodiments of process methods thatimpart stress from the sacrificial (i.e., temporary) stressed materialto one or more adjacent layers. The ability to remove the sacrificialstressed material without removing all the stress imparted to the one ormore adjacent layers addresses the above-described problems withconventional methods of imparting stress in the channel region of atransistor. The stress is imparted without needing to alter thecomposition of a semiconductor material having an incorporated dopant(e.g., a doped region of the transistor). It is also imparted withouthaving to select and permanently deposit a stressed conductive materialin the contact trenches above the semiconductor material having theincorporated dopant. Additional details about embodiments of the presenttechnology, which addresses these and other problems, is provided below.

FIG. 1 shows exemplary operations in a processing method 100 accordingto some embodiments of the present technology. The methods may beincluded in a broader development of semiconductor structures, and mayinclude additional operations to develop a structure including front-endprocessing, dummy gate formation, or any number of additional operationsto form a structure to which an induced stress may provide beneficialimpact. The method 100 may include depositing a sacrificial stressedmaterial on an adjacent layer that is between the stressed material anda semiconductor material having an incorporated dopant (e.g., a dopedregion) 105, such as a contact liner in a FinFET structure. The dopedregion may be a source region, drain region, or channel region locatedadjacent to a gate of a semiconductor device. Exemplary semiconductordevices may include semiconductor transistors, such as n-channel andp-channel MOSFETs, FinFETs, gate-all-around FETs, and nanosheet FETs,among other types of semiconductor transistors. Exemplary semiconductordevices may include bulk semiconductor (e.g., silicon) devices, andsemiconductor-on-insulator (SOI) devices.

In some embodiments, the sacrificial stressed material may becharacterized by a stress of greater than or about 1 GPa. In additionalexamples, the stressed material may be characterized by a stress ofgreater than or about 2 GPa, greater than or about 3 GPa, greater thanor about 4 GPa, greater than or about 5 GPa, greater than or about 6GPa, or more. For the purposes of this application, a higher-stressmaterials is characterized by an absolute value of stress, eitherpositive or negative, that is greater than the absolute value of alower-stress material. The convention used here is that positive stressis characterized as tensile stress, negative stress is characterized ascompressive stress, and no stress (i.e., 0 GPa) is characterized asneutral stress. Positive (i.e., tensile) stress may characterized by anoutward pushing force that may be created by the expansion of amaterial. Negative (i.e., compressive) stress may be characterized by aninward pulling force that may be created by the contraction of thematerial.

The amount of stress in the stressed material may depend on the amountof stress that should be imparted to the channel region of thesemiconductor device as a result of depositing the stressed material. Insome embodiments, this may involve a determination of the amount ofstress that remains in the one or more layers adjacent to the dopedregions of the device after the stressed material is removed. Exemplarystressed materials may include an electrically conductive material suchas tungsten, cobalt, copper, and aluminum, among other conductivematerials. Additional exemplary stressed materials may include adielectric material such as silicon oxide, silicon nitride, siliconoxycarbide, and carbon-containing organic materials, among other typesof dielectric materials. The present technology permits a selection of astressed material based primarily on its ability to generate an amountof lasting stress in adjacent layers following a heating operation. Theselection of the sacrificial stressed material does require that theamount of stress be balanced with other properties of the material, suchas its conductivity, permeability, etc., that is done for materials thatremain on the substrate. This expands the number of candidate materialsavailable to use as the stressed material, and permits the selection ofstressed materials that would otherwise be disqualified based on otherproperties.

In embodiments, the one or more adjacent layers may be characterized bya nominal viscosity at 25° C. of 1.5 × 10⁶ cP or less, 1 × 10⁶ cP orless, 5 × 10⁵ cP or less, 1 × 10⁵ cP or less, 5 × 10⁴ cP or less, 1 ×10⁴ cP or less, or less. It is thought that a lower nominal viscosity ofthe adjacent layers permits an increased amount of the stress from thestressed material to be transmitted to the adjacent layers. In manyinstances, adjacent materials that experience an increased change instress as a result of contact with the stressed material may permanentlyretain more of that increased stress following a rapid thermal anneal.Thus, the adjacent layers may be selected in part for their nominalviscosity and its effect on the incorporation and retention of stressfrom a sacrificial stressed material. In some embodiments, the adjacentlayers may include silicon oxide having a nominal viscosity at 25° C. ofabout 5.25 × 10⁴ cP, silicon nitride having a nominal viscosity at 25°C. of about 1.3 × 10⁶ cP, and/or low-k, carbon-containing spacermaterial having a nominal viscosity at 25° C. of about 5.25 × 10⁴ cP.

In embodiments, the one or more adjacent layers may be characterized bylow stress relative to their stress following the deposition, heating,and removal of the sacrificial stressed material. In some embodiments,the adjacent layers may have about neutral stress (e.g., about 0 MPastress) before the deposition of the stressed material. In additionalembodiments, the adjacent layers may have stress less than or about 100MPa, less than or about 50 MPa, less than or about 25 MPa, less than orabout 10 MPa, less than or about 5 MPa, less than or about 1 MPa, lessthan or about 0.1 MPa, or less. The present technology permits theselection and deposition of one or more adjacent layers withoutrequiring them to have a minimum about of stress. They may be formed inan as-deposited state with about neutral stress, and their stress levelincreased by the imparted and retained stress from the subsequentlydeposited stressed material.

Embodiments of the one or more adjacent layers may include materialsthat are selected based on the function of the layer. In someembodiments the one or more adjacent layers may include one or moreliner layers that serve functions at the interface between the stressedmaterial and the doped region. Embodiments of the liner layers mayinclude barrier layers to prevent, for example, a fill material in theopening from contaminating the doped region, and conversely, to preventdoping-region materials from contaminating the fill material.Embodiments of the liner layers may also include transition layers tojoin a doped region material with a fill material with improvedcompatibility between the materials. Embodiments of the liner layers mayfurther include seed layers to promote the deposition of a fill materialin the opening. Embodiments of the liner layers may still furtherinclude etch stop layers (e.g., contact etch stop layers (CESLs)) thatprevent etch operations from etching material beyond the layer.Additional embodiments of the one or more adjacent layers may include adielectric layer formed over the semiconductor material having anincorporated dopant. In some embodiments, this dielectric layer mayinclude silicon oxide, carbon-doped silicon oxide, silicon-oxynitride,and/or silicon nitride, among other dielectric materials. In someembodiments, one or more liner layers may be formed on the sidewallportions of the dielectric layer.

In some embodiments, the sacrificial stressed material may be depositedin and around a substrate feature, such as an opening. In some of theseembodiments, one or more of the adjacent layers may help frame theopening, and may make contact with the sidewalls and/or bottom of theopening. In embodiments, the opening may be a contact trench positionedadjacent to a doped region of semiconductor material such as a sourceregion, drain region, or channel region of a semiconductor transistor.The sacrificial stressed material may be deposited in the opening at afast deposition rate to increase process efficiency. Deposition ratesmay be selected that create significant numbers of voids, seams or otherdefects in the fill. In most instances, these defects are not concerningsince the stressed material will be removed from the opening after aheating operation to make permanent at least a portion of the stressimparted to the adjacent layers from the stressed material.

The method 100 may also include heating the sacrificial stressedmaterial deposited on the one or more adjacent layers 110. In someembodiments, the heating operation may include a rapid thermal anneal ofthe substrate holding the sacrificial stressed material and one or moreadjacent layers. Embodiments of the rapid thermal anneal include heatingat a heating rate greater than or about 150° C./second, greater than orabout 180° C./second, greater than or about 200° C./second, greater thanor about 300° C./second, greater than or about 400° C./second, greaterthan or about 500° C./second, greater than or about 600° C./second,greater than or about 750° C./second, greater than or about 1000°C./second, or more. In embodiments, the heating may be done by heatingthe substrate with a heat lamp, a laser, a heating element in a pedestalsupporting the substrate, or a plasma, among other heating components.In some embodiments, the heating may be done with a spike anneal thatincreases the temperature of the sacrificial stressed material at aheating rate greater than or about 150° C./second. In additionalembodiments, the sacrificial stressed material may be heated for aperiod of less than or about 5 minutes. In still further embodiments,the annealed sacrificial material may be cooled at a cooling rate ofless than or about 50° C./second. In additional embodiments, the heatingmay be done with a laser anneal that can heat one or more exposed layersof material to a temperature greater than or about 1000° C. in a periodless than or about 1 millisecond. In further embodiments, a laser annealmay locally heat the sacrificial substrate material at a heating rategreater than or about 1×10⁶ °C/second.

In some embodiments, the heating operation may involve heating targetedmaterials on regions of the substrate to a temperature greater than orabout 700° C., greater than or about 750° C., greater than or about 800°C., greater than or about 850° C., or greater than or about 950° C., ormore. This may allow anneal affects at high temperature to be imparted,while maintaining the substrate below budgeted temperatures. In someembodiments, the anneal temperature may directly affect the amount ofmemorized stress in the underlying material. By performing a spikeanneal, temperatures well beyond thermal budget requirements may beused, while limiting any damage to the underlying materials orstructure.

As noted above, a rapid thermal anneal of the sacrificial stressedmaterial and the one or more adjacent layers permits the adjacent layersto memorize at least a portion of the stress imparted by the stressedmaterial. The memorized stress is retained by the adjacent layers afterthe removal of the sacrificial stressed material. It is thought that therapid temperature changes affected by a rapid thermal anneal creates andmaintains the atomic structure in a more disordered state that helps theadjacent layers retain the imparted stress. In some embodiments, thepercentage of the initial stress imparted by the stressed material to anadjacent layer that is retained by the adjacent layer may be greaterthan or about 0.1%, greater than or about 0.3%, greater than or about0.5%, greater than or about 1%, greater than or about 2%, greater thanor about 3%, greater than or about 4%, greater than or about 5%, ormore.

The method 100 may further include removing the stressed material fromthe one or more adjacent layers 115. In some embodiments, the removalmay be done by an etch or polishing of the stressed material from thesubstrate. In embodiments, the etching processes may include wet etchingand dry etching. In further embodiments, the dry etching may include aselective plasma etch that selectively removes the sacrificial stressedmaterial over the one or more adjacent layers. In still furtherembodiments, removal of the stressed material may include chemicalmechanical polishing (CMP) of the stressed material off an exposedsurface of the substrate.

In some embodiments, the method 100 may also include depositing a secondmaterial to replace the sacrificial stressed material 120. Inembodiments, the second material may be deposited by chemical vapordeposition on the one or more adjacent layers. Embodiments of thechemical vapor deposition method may include plasma-enhanced chemicalvapor deposition, and high-density plasma chemical vapor deposition,among other CVD processes. The second material may be anelectrically-conductive material made from, for example, tungsten,cobalt, copper, aluminum, and combinations thereof, among otherconductive materials. In some embodiments, the second material may be anelectrically-conductive metal that is deposited in a contact trench,among other places on the substrate, that was formerly filled with thestressed material. The electrically-conductive metal forms at least aportion of the metal contact between a doped region of a semiconductortransistor (e.g., a source region or a drain region of the transistor)and additional conductive components such as a via interconnect and/ormetal stack interconnect.

Embodiments of the second material may be characterized by stress lessthan the stressed material it replaces. Embodiments further include asecond material characterized by stress that is lower than the stress inthe one or more adjacent layers post-anneal. For example, one or more ofthe adjacent layers may be characterized by a post-anneal stress atleast ten times greater than the second-material stress, at leastfifteen times greater than the second-material stress, at least twentytimes greater than the second-material stress, at least thirty timesgreater than the second-material stress, at least forty times greaterthan the second-material stress, at least fifty times greater than thesecond-material stress, or more. In some embodiments, the as-depositedsecond material may be characterized by a stress level of less than orabout 100 MPa, less than or about 50 MPa, less than or about 25 MPa,less than or about 10 MPa, less than or about 5 MPa, less than or about1 MPa, less than or about 0.1 MPa, or less. In some embodiments, theas-deposited second material may be characterized by about neutralstress. The present technology permits a selection of a second materialbased primarily on characteristics other than its ability to generate anamount of lasting stress in adjacent layers and doped regions of thesubstrate. For example, the second material and its deposition may beselected for its electrical conductivity to provide a low-resistance,local connect between a doped region of a semiconductor transistor andadditional conductive components in an integrated circuit.

As noted above, embodiments of the present technology may be used tofabricate semiconductor device structures, including semiconductortransistors such as n-channel and p-channel MOSFETs, FinFETs,gate-all-around FETs, and nanosheet FETs, among other types oftransistors. FIGS. 2A-C show simplified cross-sections of asemiconductor structure during selected operations in embodiments of thepresent methods. In the embodiment shown, one or more stressed materialsare replaced one or more conductive materials in three contact trenches.In other embodiments (not shown), stressed materials in one or two ofthe contact trenches may be replaced with conductive materials. FIG. 2Ashows an embodiment of a semiconductor structure 200 that includes oneor more sacrificial stressed materials 202 a-c deposited in one or morecontact trenches 204 a-c that include one or more intermediate(adjacent) layers 205 a-c. The sacrificial stressed materials 202 a-cmay be characterized by an amount of stress greater than the stress inthe intermediate layers 205 a-c at least before the stressed materials202 a-c contact the intermediate layers 205 a-c. After contact, thestress in the one or more intermediate layers 205 a-c increases from alower-stress, first stress amount to a higher-stress, second stressamount. In some embodiments, the percentage change in the stress of anintermediate layer 205 a-c from the first stress amount to the secondstress amount may be greater than or about 0.1%, greater than or about1%, greater than or about 2%, greater than or about 5%, greater than orabout 10%, greater than or about 25%, greater than or about 50%, greaterthan or about 75%, greater than or about 100%, or more. In additionalembodiments, the first stress amount in an intermediate layer 205 a-cmay be less than or about 10 MPa, less than or about 5 MPa, less than orabout 1 MPa, or less. In further embodiments, the second stress amountin an intermediate layer 205 a-c may be greater than or about 1 MPa,greater than or about 5 MPa, greater than or about 10 MPa, greater thanor about 50 MPa, greater than or about 100 MPa, or more.

The intermediate layers 205 a-c may be positioned between the one ormore stressed materials 202 a-c and a semiconductor material having anincorporated dopant, which may be described as dopant regions 206 a-c.In the embodiment shown in FIGS. 2A-C, additional materials 212 a-b and214 may be positioned between the intermediate layers 205 a-c and thedopant regions 206 a-c. In some embodiments, one or more of theseadditional materials 212 a-b and 214 may be intermediate layers that arecharacterized by an increase in stress as a result of the stressedmaterials 202 a-c. The dopant regions 206 a-c may be part of a largersubstrate, which is represented as substrate region 208. In someembodiments, the dopant region may be a source region, a drain region,or a channel region of a semiconductor transistor. A portion of theincreased stress created by the one or more stressed materials 202 a-cin one or more of the intermediate layers 205 a-c may create increasedstress in the dopant region 206. In some embodiments, the percentagechange in the stress in one or more of the dopant regions 206 a-c causedby the increased stress in the one or more intermediate layers 205 a-cmay be greater than or about 0.1%, greater than or about 1%, greaterthan or about 2%, greater than or about 5%, greater than or about 10%,greater than or about 25%, greater than or about 50%, greater than orabout 75%, greater than or about 100%, or more.

As noted above, embodiments of the present technology include theremoval of the one or more sacrificial stressed materials 202 a-c fromone or more of the intermediate layers 205 a-c. FIG. 2B shows thesubstrate structure with the one or more stressed materials 202 a-cremoved. The adjacent layers 205 a-c have retained at least a portion ofthe increased stress created by the stressed material as a result of arapid thermal anneal performed prior to the removal. In someembodiments, the percentage of the stress retained by the one or moreintermediate layers 205 a-c after removal of the one or more stressedmaterials 202 a-c may be greater than or about 5%, greater than or about10%, greater than or about 15%, greater than or about 20%, greater thanor about 30%, greater than or about 40%, greater than or about 50%,greater than or about 60%, greater than or about 70%, greater than orabout 80%, greater than or about 90%, or more.

The removal of the stressed material permits its replacement with a newmaterial that may be better suited for permanent incorporation into thesemiconductor device and integrated circuit. FIG. 2C shows one or moreelectrically-conductive materials 210 a-c replacing the one or moresacrificial stressed materials 202 a-c in one or more intermediatelayers 205 a-c. Embodiments of the one or more conductive materials 210a-c may be made from a conductive metal such as tungsten, cobalt,copper, aluminum, or combinations thereof. The one or more conductivematerials 210 a-c may be characterized by tensile stress significantlylower than that retained in the one or more intermediate layers 205 a-cor the one or more removed stressed materials 202 a-c. In someembodiments, the one or more intermediate layers 205 a-c may becharacterized by tensile stress at least ten times the stress in the oneor more conductive materials 210 a-c. In additional embodiments, thedifference in tensile stress between the one or more intermediate layers205 a-c and the one or more conductive materials 210 a-c may be greaterthan or about fifteen times, greater than or about twenty times, greaterthan or about fifty times, greater than or about one hundred times,greater than or about two hundred times, or more. In furtherembodiments, the difference in tensile stress between the one or morestressed materials 202 a-c and the one or more conductive layers 210 a-cmay be greater than or about one hundred times, greater than or abouttwo hundred times, greater than or about five hundred times, greaterthan or about one thousand times, greater than or about two thousandtimes, or more. In some embodiments, the lower stress may facilitate alower resistivity and higher conductivity in the one or more conductivematerials 210 a-c.

Embodiments of the present technology create and retain an increasedstress in an intermediate (adjacent) layer from the deposition andremoval of a sacrificial stressed material. The retained stress impartedby the intermediate layer creates increased stresses in nearby regionsof semiconductor material having an incorporated dopant, including achannel region of a semiconductor device. Increasing the stress of thechannel region may improve device performance on one or more measures.For example, the increased stress in the channel region is thought toincrease the mobility of charge carriers in the channel, which increasesthe drive current through the channel region. In some embodiments, theincreased stress created in the channel region by embodiments of thepresent technology may increase the drive current through a transistorchannel by greater than or about 1%, greater than or about 2%, greaterthan or about 3% greater than or about 4%, greater than or about 5%,greater than or about 10%, or more. An increase in drive current throughthe channel region can increase transistor performance in a number ofrespects including increased switching speed, and reduced powerconsumption, among others. Embodiments of the present technologyaccomplishes these improvements in semiconductor device performancewithout constraining the types of materials used in the devices that maycreate new processing problems or compromise device performance in otherrespects.

In the preceding description, for the purposes of explanation, numerousdetails have been set forth in order to provide an understanding ofvarious embodiments of the present technology. It will be apparent toone skilled in the art, however, that certain embodiments may bepracticed without some of these details, or with additional details.

Having disclosed several embodiments, it will be recognized by those ofskill in the art that various modifications, alternative constructions,and equivalents may be used without departing from the spirit of theembodiments. Additionally, a number of well-known processes and elementshave not been described in order to avoid unnecessarily obscuring thepresent technology. Accordingly, the above description should not betaken as limiting the scope of the technology.

Where a range of values is provided, it is understood that eachintervening value, to the smallest fraction of the unit of the lowerlimit, unless the context clearly dictates otherwise, between the upperand lower limits of that range is also specifically disclosed. Anynarrower range between any stated values or unstated intervening valuesin a stated range and any other stated or intervening value in thatstated range is encompassed. The upper and lower limits of those smallerranges may independently be included or excluded in the range, and eachrange where either, neither, or both limits are included in the smallerranges is also encompassed within the technology, subject to anyspecifically excluded limit in the stated range. Where the stated rangeincludes one or both of the limits, ranges excluding either or both ofthose included limits are also included.

As used herein and in the appended claims, the singular forms “a”, “an”,and “the” include plural references unless the context clearly dictatesotherwise. Thus, for example, reference to “a precursor” includes aplurality of such precursors, and reference to “the layer” includesreference to one or more layers and equivalents thereof known to thoseskilled in the art, and so forth.

Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”,“include(s)”, and “including”, when used in this specification and inthe following claims, are intended to specify the presence of statedfeatures, integers, components, or operations, but they do not precludethe presence or addition of one or more other features, integers,components, operations, acts, or groups.

1. A semiconductor structure comprising: a conductive layercharacterized by a first tensile stress; an intermediate layer incontact with the conductive layer, wherein the intermediate layer ischaracterized by a second tensile stress at least ten times the firsttensile stress; and a semiconductor material having an incorporateddopant, wherein the intermediate layer is disposed between theconductive layer and the semiconductor material having the incorporateddopant.
 2. The semiconductor structure of claim 1, wherein the firsttensile stress in the conductive layer is less than 1 MPa.
 3. Thesemiconductor structure of claim 1, wherein the second tensile stress inthe intermediate layer is greater than 1 MPa.
 4. The semiconductorstructure of claim 1, wherein the first tensile stress in the conductivelayer is less than 0.1 MPa.
 5. The semiconductor structure of claim 1,wherein the second tensile stress in the intermediate layer is greaterthan 50 MPa.
 6. The semiconductor structure of claim 1, wherein theconductive layer comprises tungsten, cobalt, copper, or aluminum.
 7. Thesemiconductor structure of claim 1, wherein the intermediate layercomprises silicon oxide or silicon nitride.
 8. The semiconductorstructure of claim 1, wherein the semiconductor material having anincorporated dopant comprises a source region, a drain region, or achannel region of a semiconductor transistor.
 9. The semiconductorstructure of claim 1, wherein the semiconductor structure comprises ann-channel or a p-channel MOSFET, a FinFET, a gate-all-around FET, or ananosheet FET.
 10. A semiconductor structure comprising: a substratecomprising doped source and drain regions; a conductive layercharacterized by a first tensile stress; and an intermediate layer incontact with each of the conductive layer and the substrate, wherein theintermediate layer is characterized by a second tensile stress at leastfifteen times the first tensile stress.
 11. The semiconductor structureof claim 10, wherein the first tensile stress in the conductive layer isless than 1 MPa.
 12. The semiconductor structure of claim 10, whereinthe second tensile stress in the intermediate layer is greater than 1MPa.
 13. The semiconductor structure of claim 10, wherein the firsttensile stress in the conductive layer is less than 0.1 MPa.
 14. Thesemiconductor structure of claim 10, wherein the second tensile stressin the intermediate layer is greater than 50 MPa.
 15. The semiconductorstructure of claim 10, wherein the conductive layer comprises tungsten,cobalt, copper, or aluminum.
 16. The semiconductor structure of claim10, wherein the intermediate layer comprises silicon oxide or siliconnitride.
 17. The semiconductor structure of claim 10, wherein thesemiconductor structure comprises an n-channel or a p-channel MOSFET, aFinFET, a gate-all-around FET, or a nanosheet FET.